By Arno Becker
Java-erfahrene Leser lernen in diesem Buch, hochwertige software program für die Android-Plattform zu entwickeln. Im ersten Teil des Buches lernt der Leser zunächst die grundlegenden Konzepte und Elemente von Android kennen. Im anschließenden Praxisteil kann er anhand eines durchgängigen Beispiels Schritt für Schritt die Entwicklung einer mobilen Anwendung nachvollziehen. Der dritte Teil bereitet Entwickler auf den professionellen und sicheren Einsatz von Android in der Praxis vor.
Die 2. Auflage wurde komplett auf die Android-Version 2 aktualisiert und um neue Themen erweitert (Live Folder, Kamera- und Video-Unterstützung, SMS senden und empfangen).
Read Online or Download Android 2: Grundlagen und Programmierung PDF
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Extra resources for Android 2: Grundlagen und Programmierung
Ishii Fig. 8 Energy consumptions per FLOP of DGEMM. “ALU/FPU” is the energy consumption for arithmetic unit. “RF/VAR” is energy consumption for the register file and vector arithmetic register file. “D$/VDR” is energy consumption for the on-chip cache, the vector data register, and the onchip network. “I$/Sched” is the energy for the instruction fetching and scheduling. “MEM” is the energy for off-chip memory access. We estimate the energy for processor chip only. Therefore, this estimation does not include any other device such as the inter-node interconnects For further investigation, we analyze the detail of the energy consumption.
Therefore, large components should be partitioned into sub-circuits without dividing its critical-path, and small components should be packed together into one layer. To keep the footprint of 3-D stacked VLSIs small, the size of each layer should be equalized. If one sub-circuit is larger than other sub-circuits, it enlarges the footprint of 3-D stacked VLSI. This equalization is controlled and achieved by partitioning large components. 40 R. Egawa et al. Fig. 3 Design flow of 3-D stacked arithmetic units h at lp ca iti h at lp Logic Depth cr ca Output iti Combinational Logic Circuit Input cr h at lp ca iti cr Logic Depth Input Output Fig.
Chen. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In DAC ’08: Proceedings of the 45th annual Design Automation Conference, pages 554–559, New York, NY, USA, 2008. ACM. 6. R. Egawa, Y. Funaya, R. Nagaoka, Y. Endo, A. Musa, H. Takizawat, and H. Kobayashi. Effects of 3-D Stacked Vector Cache on Energy Consumption. In 2011 IEEE International 3D Systems Integration Conference (3DIC), pages 1–8, 2012. 7. Y. Funaya, R. Egawa, H. Takizawat, and H.